Designing efficient translation lookaside buffers. 3. Multi-core and Parallel Processors
Handling memory dependencies and hardware-level recovery during mispredictions. Memory Hierarchy and Thread-Level Parallelism (TLP)
Prof. Sarangi provides a complete ecosystem for this course: Textbook (PDF): The full digital version of Next-Gen Computer Architecture Lecture Slides: Downloadable PPTX files are available on the course website Video Lectures: You can watch the accompanying lecture series on the NPTEL YouTube channel or via the Swayam platform Foundational Text: If you need the introductory level first, his Basic Computer Architecture PDF is also free. Key Topics Covered The advanced text is divided into three major parts: Processor Design:
As single-core scaling reached its physical limits, the industry shifted to multicore designs. The text provides deep mathematical and structural insights into: advanced computer architecture smruti r sarangi pdf top
Out-of-order pipelines, advanced branch prediction, fetch/decode stages, and issue/execute/commit logic. The Memory System
Memory layout dictates overall system performance. The resource deep-dives into non-blocking caches, victim caches, and advanced cache allocation techniques. It also introduces Virtual Memory management and Translation Lookaside Buffer (TLB) hierarchies optimized for massive datasets. 4. Hardware-Software Co-Design
The book "Advanced Computer Architecture" by Smruti R Sarangi is organized into the following chapters: Designing efficient translation lookaside buffers
Eliminating Write-After-Read (WAR) and Write-After-Write (WAW) hazards using Tomasulo’s algorithm and Reorder Buffers (ROB).
The "story" transitions into how data moves, detailing cache design, on-chip networks (NoCs), and multicore coherence. Specialized Hardware: It includes dedicated chapters on and high-speed main memory technologies like DDR-4. The Future ("Till the End of Silicon"):
Deep technical analysis of MSI, MESI, and MOESI protocols in multi-core systems, including directory-based vs. snooping mechanisms. Memory Hierarchy and Thread-Level Parallelism (TLP) Prof
: Prof. Sarangi has made the PDF versions of his textbooks—both Basic Computer Architecture
The final sections address modern critical issues such as hardware security, power management, reliability, and the burgeoning field of AI/ML accelerators Open Access Initiative
A unique strength of Sarangi's methodology is the emphasis on compiler-architecture interaction. It explains how compilers optimize code for specific hardware features like Very Long Instruction Word (VLIW) processors and Explicitly Parallel Instruction Computing (EPIC). Key Learning Outcomes